1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and more particularly, to a method of fabricating a semiconductor device equipped with a diamond substrate and a device structure such as a Gallium Arsenide (GaAs) Field-Effect Transistor (FET) or FETs and a method of fabricating the semiconductor device, which provides improvement in heat dissipation performance.
2. Description of the Prior Art
With high-output semiconductor devices, a lot of heat is generated in the devices on operation and therefore, the output level lowering and/or the reliability degradation tend to occur due to the heat. The devices themselves may be damaged due to the heat. In particular, since GaAs has a higher thermal resistance than that of silicon (Si), GaAs FETs have a low heat dissipation performance than Si FETs. Thus, to improve the performance of high-output GaAs devices, it is essential to make the heat dissipation performance as high as possible.
The Japanese Non-Examined Patent Publication No. 5-166899 published in 1993 discloses a semiconductor device of this sort, which is shown in FIG. 1.
The prior-art semiconductor device of FIG. 1 is comprised of a semi-insulating GaAs substrate 600 polished to have a thickness of 30 xcexcm. An n-type active layer 601 is formed in the surface area of the GaAs substrate 600. On the surface area of the substrate 600, a source electrode 602a, a drain electrode 602b, and a gate electrode 603 are formed. The source electrode 602a is located to overlap with one end of the active layer 601. The drain electrode 602b is located to overlap with the other end of the active layer 601. The gate electrode 603 is located approximately in the middle of the active layer 601. The active layer 601, the source and drain electrodes 602a and 602b, and the gate electrode 603 constitute a GaAs FET structure 609.
A lot of grooves 608, each of which has a depth of 2 xcexcm and a width of 2 xcexcm, are formed on the back surface of the GaAs substrate 600 by etching to overlap with the whole active layer 601, thereby increasing the surface area of the back surface of the GaAs substrate 600.
A Plated Heat Sink (PHS) 607 with a thickness of 30 xcexcm is fixed to the grooved back surface of the substrate 600. The PHS 607 is made of gold (Au) and fixed by a plating process.
Because of the increased interface area of the GaAs substrate 600 and the PHS 607, the heat dissipation performance of the semiconductor device of FIG. 1 is enhanced without changing the dimension or size of the device.
However, the above-described prior-art semiconductor device of FIG. 1 has a problem that the temperature at the interface of the substrate 600 and the PHS 607 is scarcely changed. This problem is caused by the fact that the thickness of the GaAs substrate 600 is scarcely changed although the contact area of the substrate 600 and the PHS 607 is increased by formation of the grooves 608 to thereby enhance the thermal conductivity and the heat dissipation effect.
This point is explained in detail below.
Here, the area of the channel region of the FET structure 609 is defined as A1 and it is supposed that all the heat generated in the channel region is propagated to the PHS 607. Then, the thermal flux Q1 of the GaAs substrate 600 per unit time in the steady state is expressed by the following equation (1)                               Q          1                =                                            k              1                        ⁡                          (                                                θ                  1                                -                θ                            )                                ⁢                      xe2x80x83                    ⁢                                    A              1                                      δ              1                                                          (        1        )            
where k1 is the thermal conductivity of the substrate 600, xcex41 is the thickness of the substrate 600, xcex81 is the temperature of the heat source (i.e., the channel region), and xcex8 is the temperature at the interface of the substrate 600 and the PHS 607.
The thermal flux Q2 of the PHS 607 per unit time in the steady state is expressed by the following equation (2)                               Q          2                =                                            k              2                        ⁡                          (                              θ                -                                  θ                  2                                            )                                ⁢                      xe2x80x83                    ⁢                                    A              2                                      δ              2                                                          (        2        )            
where A2 is the area of the interface of the substrate 600 and the PHS 607, k2 is the thermal conductivity of the PHS 607, xcex42 is the thickness of the PHS 607, and xcex82 is the temperature at the outer surface of the PHS 607 contacting with the atmosphere.
When the thermal conductivity, the thickness, and the cross-sectional area of a material are defined as k, xcex4, and A, respectively, the thermal resistance R of the material is generally given by                     R        =                  δ          kA                                    (        3        )            
Therefore, the following equations (4) and (5) are established.                               R          1                =                              δ            1                                              k              1                        ⁢                          A              1                                                          (        4        )                                          R          2                =                              δ            2                                              k              2                        ⁢                          A              2                                                          (        5        )            
Therefore, by using the equations (4) and (5), the above-described equations (1) and (2) are rewritten to as follows.                               Q          1                =                                            θ              1                        -            θ                                R            1                                              (                  1          xe2x80x2                )                                          Q          2                =                              θ            -                          θ              2                                            R            2                                              (                  2          xe2x80x2                )            
Considering the flow of heat in the steady state, Q1=Q2 is established. Also, it is supposed that the substrate 600 and the PHS 607 are equal in thickness and area to each other, the temperature xcex8 at the substrate-PHS interface is given as a function of the thermal conductivities k1 and k2 and temperatures xcex81 and xcex82 as follows.                     θ        =                                                            k                1                            ⁢                              θ                1                                      +                                          k                2                            ⁢                              θ                2                                                                        k              1                        +                          k              2                                                          (        6        )            
When xcex81=100xc2x0 C., xcex82=40xc2x0 C., k1=0.46 W/cmxc2x0 C., and k2=3.2 W/cmxc2x0 C., the equation (6) gives xcex8=47.5xc2x0 C.
The above explanation is applied to the case where the grooves 608 are omitted in the prior-art semiconductor device of FIG. 1. On the other hand, with the prior-art semiconductor device of FIG. 1 having the grooves 608, the temperature xcex8 at the interface of the substrate 600 and the PHS 607 is given as follows.
It is supposed that the contact area Am of the substrate 600 and the PHS 607 is twice as much as that of the above-described case where the grooves 608 are omitted (i.e., Am=2A1) while the area A1 of the channel region is unchanged. Then, the thermal conduction from the area A1 to the area Am (=2A1) is approximated to the planar conduction model of heat by using the logarithmically averaging conversion method, resulting in the following equation (7)                               Q          1                =                                            k              1                        ⁡                          (                                                θ                  1                                -                θ                            )                                ⁢                                    A              m                                      δ              1                                                          (        7        )            
where the area Am is given by the following expression (8).                               A          m                =                                            A              1                                      ln              ⁡                              (                2                )                                              ≅                      1.44            ⁢                          A              1                                                          (        8        )            
It is supposed that the PHS 607 has a heat dissipation area twice as much as that of the area A1. Then, the following equation (9) is obtained.                               Q          2                =                                            k              2                        ⁡                          (                              θ                -                                  θ                  2                                            )                                ⁢                      xe2x80x83                    ⁢                                    2              ⁢                              A                1                                                    δ              2                                                          (        9        )            
Since Q1=Q2 is established in the steady state, the following equation (10) is obtained.                     θ        =                                            1.44              ⁢                              k                1                            ⁢                              θ                1                                      +                          2              ⁢                              k                2                            ⁢                              θ                2                                                                        1.44              ⁢                              k                1                                      +                          2              ⁢                              k                2                                                                        (        10        )            
When xcex81=100xc2x0 C., xcex82=40xc2x0 C., k1=0.46 W/cmxc2x0 C., and k2=3.2 W/cmxc2x0 C., which is the same condition as that of the above-described equation (6), the equation (10) gives xcex8=45.6xc2x0 C.
As seen from this result, even if the interface area (or contact area) of the GaAs substrate 600 and the PHS 607 is twice as much as that of the case where the grooves 608 are omitted, the temperature xcex8 at the substrate-PHS interface is decreased by only approximately 2xc2x0 C. In other words, the temperature lowering rate (i.e., temperature gradient) in the GaAs substrate 600 is as low as 1.81xc2x0 C./xcexcm.
Accordingly, an object of the present invention to provide a semiconductor device having a decreased thermal resistance and a method of fabricating the semiconductor device.
Another object of the present invention to provide a semiconductor device having an improved heat dissipation performance and a method of fabricating the semiconductor device.
Still another object of the present invention to provide a semiconductor device having an improved radio-frequency (RF) characteristics and a method of fabricating the semiconductor device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a semiconductor device is provided, which is comprised of a diamond substrate having a main surface, a semiconductor base or supporting layer attached onto the main surface of the diamond substrate, and a device structure formed on the semiconductor base layer.
With the semiconductor device according to the first aspect of the present invention, the device structure, which is formed on the semiconductor base layer, is located on the main surface of the diamond substrate. The diamond substrate has a thermal conductivity higher than that of a semiconductor substrate such as a GaAs substrate. Thus, the total thermal resistance of the semiconductor device according to the first aspect of the present invention is decreased compared with a semiconductor device equipped with a semiconductor substrate. In other words, the semiconductor device according to the first aspect of the present invention has an improved heat dissipation performance.
Also, since the diamond substrate has a better electrical insulation property than a semiconductor substrate, the semiconductor device according to the first aspect of the present invention has an improved RF characteristics.
In the device according to the first aspect, as the diamond substrate, any diamond substrate having a good electrical insulating property may be used. The diamond substrate may be natural or artificial.
In a preferred embodiment of the device according to the first aspect, the semiconductor base layer is fixed to the main surface of the substrate by physical absorption or an intermolecular force such as a van der Waals force.
In another preferred embodiment of the device according to the first aspect, the device structure is a FET structure having a semiconductor active layer formed on or in the semiconductor base layer, a source electrode contacted with one end of the active layer, a drain electrode contacted with the other end of the active layer, and a gate electrode contacted with the active layer between the source and drain electrodes.
In still anther preferred, embodiment of the device according to the first aspect, the diamond substrate has a heat sink attached to a back surface of the diamond substrate.
According to a second aspect of the present invention, a method of fabricating a semiconductor device is provided, which is comprised of the following steps (a) to (d).
(a) A semiconductor base or supporting layer is formed over a main surface of a semiconductor substrate.
(b) At least one device structure is formed on the semiconductor base layer.
(c) The semiconductor base layer on which the at least one device structure has been formed is separated from the main surface of the semiconductor substrate.
(d) The semiconductor base layer on which the at least one device structure has been formed and separated from the main surface of the semiconductor substrate is attached onto a main surface of a diamond substrate. The semiconductor base layer thus attached is fixed to the main surface of the diamond substrate.
With the method according to the second aspect of the present invention, the semiconductor device according to the first aspect is fabricated.
In a preferred embodiment of the method according to the second aspect, the semiconductor base layer is formed over the main surface of the semiconductor substrate through an intervening sacrificial layer in the step (a). Also, the semiconductor base layer is separated from the main surface of the semiconductor substrate by removing the sacrificial layer in the step (c).
In another preferred embodiment of the method according to the second aspect, the semiconductor base layer is fixed to the main surface of the diamond substrate by physical absorption or an intermolecular force such as a van der Waals force in the step (d).
In still another preferred embodiment of the method according to the second aspect, a plurality of the device structures are formed on the semiconductor base layer in the step (b). The plurality of the device structures are divided from each other by dicing the semiconductor base layer and the semiconductor substrate prior to the step (c).
According to a third aspect of the present invention, another method of fabricating a semiconductor device is provided, which is comprised of the following steps (axe2x80x2) to (dxe2x80x2).
(axe2x80x2) A semiconductor base or supporting layer is formed over a main surface of a semiconductor substrate.
(bxe2x80x2) The semiconductor base layer is separated from the main surface of the semiconductor substrate.
(cxe2x80x2) The semiconductor base layer that has been separated from the main surface of the semiconductor substrate is attached onto a main surface of a diamond substrate. The semiconductor base layer thus attached is fixed to the main surface of the diamond substrate.
(dxe2x80x2) At least one device structure is formed on the semiconductor base layer that has been fixed to the main surface of the diamond substrate.
With the method according to the third aspect of the present invention, the semiconductor device according to the first aspect is fabricated.
In a preferred embodiment of the method according to the third aspect, the semiconductor base layer is formed over the main surface of the semiconductor substrate through an intervening sacrificial layer in the step (axe2x80x2). Also, the at least one device structure is separated from the main surface of the semiconductor substrate by removing the sacrificial layer in the step (bxe2x80x2).
In another preferred embodiment of the method according to the third aspect, the semiconductor base layer is fixed to the main surface of the diamond substrate by physical absorption or an intermolecular force such as a van der Waals force in the step (cxe2x80x2).
In still another preferred embodiment of the method according to the third aspect, a plurality of the device structures are formed on the semiconductor base layer in the step (dxe2x80x2). The plurality of the device structures are divided from each other by dicing the semiconductor base layer and the diamond substrate next to the step (dxe2x80x2).